Logic Fruit Technologies Launches IP Core for Avionics Applications

The new ARINC 818 IP from Logic Fruit Technologies is designed for high bandwidth, low-latency, uncompressed digital video transmission in avionics systems with a transmission rate of up to 4.25 Gbps By DA Reporter / 09 Jun 2021

Logic Fruit Technologies has released the ARINC 818 IP Core designed for advanced performance in data-intensive field-programmable gate arrays (FPGAs) with added support to a variety of functionalities such as the Cockpit Display Systems (CDS), the Head-Up Display (HUD), and Video Recording. 

ARINC 818 IP is an Avionics Digital Video Bus (ADVB) and is a high data rate video protocol simplified version of Fibre Channel (FC) protocol with an emphasis given to cost reduction and speeding up the link initialization. 

ARINC 818 IP core is a video interface and protocol standard developed for high bandwidth, low latency digital video transmission able to support transmission rates of up to 4.25 Gbps.

The IP is built on the Fiber Channel Audio Video (FC-AV defined in ANSI INCITS 356-2002) protocol which is used extensively on video systems in the F-18 and the C-130 AMP and various avionics with the added advantage of standardized implementation. This IP core is CEMILAC certified and has a DO-254 DAL-B Compliant design.

The IP core can be configured as a transmitter, as a receiver, or both transmitter and receiver in the same module. It has support for both the progressive and the interlaced video formats with other features built-in such as line-synchronous transmission, container header, and ancillary data monitoring which makes it suited to high-end applications in the silicon ICs, aircraft, and satellite industry. 

Without making any changes in the RTL code, the same IP can be used with the Optical and the Electrical interfaces.

Sanjeev Kumar, the CEO of Logic Fruit Technologies said, “The modular architecture allows high-speed communication and workload accelerators, such as GPUs, FPGAs, and other purpose-built devices, to be easily integrated with any FPGA design and transceiver modules.”

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